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IDT74ALVC1G00 3.3V CMOS SINGLE 2-INPUT POSITIVE-NAND GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS SINGLE 2-INPUT POSITIVE-NAND GATE
FEATURES:
0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) - 0.65mm pitch PSOP package - Extended commercial range of - 40C to + 85C - VCC = 3.3V 0.3V, Normal Range - VCC = 1.65V to 3.6V, Extended Range - VCC = 2.5V 0.2V - CMOS power levels (0.4 W typ. static) - Rail-to-Rail output swing for increased noise margin Drive Features for ALVC1G00: - High Output Drivers: 24mA - Suitable for heavy loads - -
IDT74ALVC1G00
DESCRIPTION:
This single 2-input positive-NAND gate is built using advanced dual metal CMOS technology. The ALVC1G00 is designed for 1.65V to 3.6V VCC operation and performs the Boolean function Y = A * B or Y = A + B in positive logic. The ALVC1G00 has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
APPLICATIONS:
* 3.3V High Speed Systems * 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1 4 2
PIN CONFIGURATION
A
Y
A B GND
1 2 3
5
VCC
B
SO5-1
4
Y
PSOP TOP VIEW
PIN DESCRIPTION
Pin Names A, B Y Description Data Inputs Data Output
FUNCTION TABLE (1)
Inputs A H L X
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care
B H X L
Output Y L H H
EXTENDED COMMERCIAL TEMPERATURE RANGE
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c 1999 Integrated Device Technology, Inc.
FEBRUARY 2000
DSC-4739/-
IDT74ALVC1G00 3.3V CMOS SINGLE 2-INPUT POSITIVE-NAND GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATING
Symbol VTERM(2) VTERM(3) TSTG IOUT IIK IOK ICC ISS Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND
(1)
Unit V V
CAPACITANCE (TA = +25oC, f = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
ALVC 1G Link
Max. - 0.5 to + 4.6 -0.5 to VCC + 0.5 - 65 to + 150 - 50 to + 50 50 - 50 100
CI/O C mA mA mA mA
NOTE: 1. As applicable to the device type.
ALVC 1G Link
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = - 40C to +85C, VCC = 2.3V to 3.6V
Symbol VIH Parameter Input HIGH Voltage Level Test Conditions VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VIL Input LOW Voltage Level VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = - 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Min. 0.65 x VCC 1.7 2 -- -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- -- -- - 0.7 100 0.1 Max. -- -- -- 0.35 x VCC 0.7 0.8 5 5 10 10 - 1.2 -- 10 A A V mV A A V Unit V
Quiescent Power Supply Current Variation
--
--
750
A
ALVC 1G Link
NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient.
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IDT74ALVC1G00 3.3V CMOS SINGLE 2-INPUT POSITIVE-NAND GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage Test Conditions(1) VCC = 1.65V to 3.6V IOH = - 0.1mA VCC = 1.65V VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3.0V VCC = 3.0V VOL Output LOW Voltage VCC = 1.65V to 3.6V VCC = 1.65V VCC = 2.3V VCC = 2.7V VCC = 3.0V IOH = - 24mA IOL = 0.1mA IOL = 4mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA -- -- -- -- IOH = - 4mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 1.2 2 1.7 2.2 2.4 2 -- -- -- -- -- -- 0.2 0.45 0.4 0.7 0.4 0.55
ALVC 1G Link
Max. --
Unit V
V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OPERATING CHARACTERISTICS, TA = 25oC
VCC = 1.8V 0.15V Symbol CPD Parameter Power Dissipation Capacitance Test Conditions CL = 0pF, f = 10Mhz Typical VCC = 2.5V 0.2V Typical 5 VCC = 3.3V 0.3V Typical 6 Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 1.8V 0.15V Symbol tPLH tPHL Parameter Propagation Delay A or B to Y Min. 1 Max. 8 VCC = 2.5V 0.2V Min. 1 Max. 3.8 VCC = 2.7V Min. Max. 3.6 VCC = 3.3V 0.3V Min. 1 Max. 3.2 Unit ns
NOTE: 1. See test circuits and waveforms. TA = - 40C to + 85C.
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IDT74ALVC1G00 3.3V CMOS SINGLE 2-INPUT POSITIVE-NAND GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS: TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V 0.3V 6 2.7 1.5 300 300 50 VCC(1) = 2.7V 6 2.7 1.5 300 300 50 VCC(2)= 2.5V 0.2V Unit 2 x Vcc V Vcc Vcc / 2 150 150 30 V V mV mV pF OPPOSITE PHASE ALVC 1G Link INPUT TRANSITION
tPLH tPHL SAME PHASE INPUT TRANSITION tPLH OUTPUT tPHL VIH VT 0V VOH VT VOL VIH VT 0V
ALVC 1G Link
TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 Pulse Generator
(1, 2)
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT SW ITCH NORMALLY CLO SED LOW tPZH OUTPUT SW ITCH NORMALLY OPE N HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
ALVC 1G Link
VLOAD Open GND
VIN D.U.T.
VOUT
RT
500 CL
ALVC 1G Link DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD
SET-UP, HOLD, AND RELEASE TIMES
DATA INPUT TIMING INPUT tREM ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL tSU tH VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
ALVC 1G Link
GND Open
ALVC 1G Link
tSU
tH
PULSE WIDTH
LOW -HIGH-LOW PULSE tW HIGH-LOW -HIGH PULSE VT
ALVC 1G Link
VT
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IDT74ALVC1G00 3.3V CMOS SINGLE 2-INPUT POSITIVE-NAND GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
1.8V 0.15V TEST CIRCUITS AND WAVEFORMS: TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 1.8V 0.15V 2 x VCC VCC VCC / 2 150 150 30 Unit V V V mV mV pF
ALVC 1G Link
SA M E PHA SE INPU T TRA NSITIO N tPLH O UTPUT tPLH O PPO SITE PHA SE INPU T TRA NSITIO N tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
ALVC 1G Link
TEST CIRCUITS FOR ALL OUTPUTS
V CC V LOAD O pen 1000 Pulse G enerator
(1)
ENABLE AND DISABLE TIMES
ENA BLE CO NTRO L INPU T tPZL O UTPUT SW ITCH NO RMA LLY CLO SED LO W tPZH O UTPUT SW ITCH NO RMA LLY OPEN HIG H VLOAD/2 VT tPHZ VT 0V tPLZ DISA BLE VIH VT 0V VLOAD/2 VLZ VOL V OH VHZ 0V
ALVC 1G Link
G ND
V IN D.U.T.
V OUT
RT
CL
1000
DEFINITIONS: ALVC 1G Link CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTE: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SET-UP, HOLD, AND RELEASE TIMES SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD
DATA INPU T TIM ING INPU T tREM AS YNCHRO NOUS CO NTRO L
ALVC 1G Link
tSU
tH
GND Open
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
ALVC 1G Link
SY NCHRO NOUS CO NTRO L
tSU
tH
PULSE WIDTH
LO W -HIG H-LO W PULSE tW HIG H-LO W -HIGH PULSE VT
ALVC 1G Link
VT
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IDT74ALVC1G00 3.3V CMOS SINGLE 2-INPUT POSITIVE-NAND GATE
EXTENDED COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX Temp. Range ALVC XXX Device Type XX Package
DY
Plastic Small Outline Package (SO5-1)
1G00
Single 2-Input Positive-NAND Gate, 24mA
74
- 40C to +85C
PICOGATE-LOGIC (DY) PACKAGES
Due to their small size, PicoGate-Logic packages require more complex symbolization guidelines. IDT's 5-pin PSOP (DY) packaged devices utilize a three-symbol name rule. The first symbol denotes device technology, the second symbol denotes device function, and the third symbol denotes a wafer fab/assembly site code for internal tracking.
EXAMPLES: 1. A PicoGate-Logic device with package code LR* is an IDT74LVC1G79A. 2. A PicoGate-Logic device with package code GC* is an IDT74ALVC1G04.
PICOGATE-LOGIC (DY) PACKAGE SYMBOLIZATION GUIDELINES TECHNOLOGY ALVC ALVCH LVC LVCH(1) CODE G J L FUNCTION 00 02 04 U04 06 07 08 14 32 79 86 125 126 132 CODE A B C D T V E F G R H M N Y
NOTE: 1. Code to be determined.
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